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SEMESTER – IV

ELECTRONIC LOGIC CIRCUIT DESIGN EC - 4003


Course Code
EC - 4003

Credits : 4

L-3, T-1, P-0

Name of the Course
Electronic Logic Circuit Design

Lectures to be delivered

52 (1 Hr Each) (L = 39, T = 13 for each semester)

Semester End Examination

Max. Time = 3 hrs.

Max. Marks: 100

Min. Pass Marks: 40

Continuous Assessment (based on sessional tests (2) 50%, Tutorials/Assignments 30%, Quiz/Seminar 10%, Attendance 10%)

Max. Marks: 50

INSTRUCTIONS


  1. For Paper Setters: The question paper will consist of five sections A, B, C, D & E. Section E will be compulsory, it will consist of a single question with 10-20 subparts of short answer type, which will cover the entire syllabus and will carry 40% of the total marks of the semester end examination for the course. Section A, B, C & D will have two questions from the respective sections of the syllabus and each question will carry 15% of the total marks of the semester end examination for the course.
  2. For candidates: Candidates are required to attempt five questions in all selecting one question from each of the sections A, B, C & D of the question paper and all the subparts of the questions in Section E. Use of non-programmable calculators is allowed.


SECTION – A

INTRODUCTION: The switching circuit, classification of switching circuits.

SEQUENTIAL CIRCUITS: Asynchronous and synchronous circuits, state diagram and state table.

SECTION – B

SEQUENTIAL LOGIC DESIGN: Introduction, register, application of shift register, ripple or asynchronous counters, synchronous counters, up-down counters, modulo counters, Decade counter. Design of counters (Binary & non-Binary)

SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN: Sequential circuits, introductory example, finite state model – Basic definition, capabilities and limitation of finite state machines, state equivalence & machine minimization, simplification of incompletely specified machines, Extraction of maximal compatibles, synthesis & analysis of synchronous sequential circuits.

SECTION – C

DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUITS: Introduction to asynchronous circuits, timing diagram, state diagram & flow tables, fundamental mode circuits, synthesis, state assignment in asynchronous sequential circuits, pulse mode circuits.

SECTION – D

HAZARDS: Introduction, gate delays, generation of spikes, production of static hazards in combinational networks, elimination of static hazards, design of hazard free combinational networks, hazard free asynchronous circuit design, dynamic hazards, essential hazards.

DECOMPOSITION OF SEQUENTIAL SYSTEMS: Advantage of modularity, types of decomposition, conditions for serial and parallel decomposition.

BOOKS:

  1. Switching and finite automata theory – ZVI Kohavi.

  2. Logical design of switching circuits – Douglas Lewin.

SEMESTER – IV


NETWORK ANALYSIS AND SYNTHESIS EC - 4004

Course Code

EC – 4004

Credits : 4

L-3, T-1, P-0

Name of the Course
Network Analysis and Synthesis

Lectures to be delivered

52 (1 Hr Each) (L = 39, T = 13 for each semester)

Semester End Examination

Max. Time = 3 hrs.

Max. Marks: 100

Min. Pass Marks: 40

Continuous Assessment (based on sessional tests (2) 50%, Tutorials/Assignments 30%, Quiz/Seminar 10%, Attendance 10%)

Max. Marks: 50

INSTRUCTIONS


  1. For Paper Setters: The question paper will consist of five sections A, B, C, D & E. Section E will be compulsory, it will consist of a single question with 10-20 subparts of short answer type, which will cover the entire syllabus and will carry 40% of the total marks of the semester end examination for the course. Section A, B, C & D will have two questions from the respective sections of the syllabus and each question will carry 15% of the total marks of the semester end examination for the course.
  2. For candidates: Candidates are required to attempt five questions in all selecting one question from each of the sections A, B, C & D of the question paper and all the subparts of the questions in Section E. Use of non-programmable calculators is allowed.


SECTION A

TRANSIENT RESPONSE: Transient Response of RC, RL, RLC Circuits to various excitation signals such as step, ramp, impulse and sinusoidal excitations using lap lace transform.

NETWORK FUNCTIONS: Terminal pairs or Ports, Network functions for one-port and two-port networks, poles and zeros of Network functions, restrictions on pole and zero locations for driving points functions and transfer functions, Time domain behavior from the pole zero plot.

SECTION B

CHARACTERISTICS AND PARAMETERS OF TWO PORT NETWORKS: Relationship of two-port variables, short-circuit Admittance parameters, open circuit impedance, parameters, Transmission parameters, hybrid parameters, relationships between parameter sets, Inter connection of two port networks.

SECTION C

TOPOLOGY: Principles of network topology, graph matrices, network analysis using graph theory.

TYPES OF FILTERS AND THEIR CHARACTERISTICS: Filter fundamentals, high-pass, low-pass, band-pass and band-reject Filters.

SECTION D

NETWORK SYNTHESIS: Positive real functions, synthesis of one port and two port networks, elementary ideas of Active networks.


TEXT BOOKS:

  1. Network Analysis & Synthesis : Umesh Sinha; Satya Prakash Pub.

  2. Network Analysis & Synthesis : F.F.Kuo; John Wiley & sons Inc.


REFERENCE BOOKS:

  1. Introduction to modern Network Synthesis : Van Valkenburg John Wiley.

  2. Network Analysis : Van Valkenburg; PHI.

  3. Basic circuit theory : Dasoer Kuh, Mc Graw Hill.

  4. A course in Electrical Circuit Analysis by Soni & Gupta; Dhanpat Rai Publication.

  5. Circuit Analysis : G.K.Mittal; Khanna Publication.
  6. Networks and systems : D.Roy Choudhary; New Age International


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